Reconfigurable FPGA
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PXI Express High Speed Optical FPGA Board
HSS-8324-DSP
The Conduant HSS-8324 FPGA board provides a user programmable hardware platform that is able to sustain full-duplex high-bandwidth transfers through its 8-lane Gen3 PXI Express (PXIe) interface and its two 12-lane HSS interfaces while performing complex calculations. The PXIe interface provides a theoretical maximum throughput of 8 GBps (simultaneous in and out) while each HSS port (12 lanes up to 16 Gbps per lane) supports a full duplex transfer at theoretical rates over 190 Gbps.
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Xilinx Zynq ARM + FPGA SoM
TE0715-7015
Sundance Multiprocessor Technology Ltd.
TE0715s are industrial-grade Xilinx Zynq-7000 System on Modules with 4 MGT Links , a gigabit Ethernet transceiver, 8 Gbit (1 Gbyte) DDR3 SDRAM with 32-bit width, 32 Mbyte SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.
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LVDS Digital I/O with Virtex-6 FPGA - XMC
Model 71610
- 32 bits of LVDS digital I/O- One LVDS clock- One LVDS data valid- One LVDS data suspend- Supports LXT and SXT Virtex-6 FPGAs- DMA controller moves data to and from system memory- Up to 2 GB of DDR3 SDRAM- PCI Express Interface- Optional user-configurable gigabit serial interface- Optional LVDS connections to the Virtex-6 FPGA for custom I/O to the carrier board- RoHS Compliant Lead-Free Version Available
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PC-Based Reconfigurable Inner Ship Modeling
PRISM
Textron Systems' PRISM is used to model the user’s platform under training, providing the student the ability to “see” the environment surrounding the equipment. With PRISM, users can script malfunctions, set initial conditions, supply evaluation results, and allow the equipment layout to be tailored to meet training objectives, which more closely matches a real-platform configuration. PRISM can be seamlessly combined with FORTRIS™, which provides the comprehensive physical and electromagnetic environment outside the platform, giving the user a complete end-to-end training experience.
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FPGA Image Processing (IP) Development Kit
ProcVision
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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Quad Serial FPDP Interface with Virtex-6 FPGA - 6U VPX
Model 57611
- Four or eight channels of serial FPDP interface- Fully compliant with VITA 17.1specification- Fiber optic or copper serial interfaces- One or two Virtex-6 FPGAs- Up to 2 or 4 GB of DDR3 SDRAM- PCI Express interface up to x8- Optional LVDS connections to the Virtex-6 FPGA for custom I/O- Ruggedized and conduction-cooled versions available
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FPGA with Digital I/O PCIe Mini Card
TMPE623
The TMPE623 is a standard full PCI Express Mini Card, providing a user programmable Xilinx Artix-7 7A50T FPGA.
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NI-9149, 8-Slot, Zynq-7020 FPGA, Ethernet CompactRIO Chassis
783376-02
8-Slot, Zynq-7020 FPGA, Ethernet CompactRIO Chassis - The NI‑9149 is a rugged Ethernet chassis that you can use to add C Series I/O modules to any standard Ethernet network. You can program the chassis using Scan Mode for fast expansion of your real-time system or using the onboard FPGA for inline processing and high-speed I/O and control. With the NI‑9149, you can add high-performance I/O to your PC-based application or expand your CompactRIO, PXI, or industrial controller application.
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400 MHz to 4.4 GHz, GPS-Disciplined OCXO, Reconfigurable USRP Software Defined Radio Device
783927-01
400 MHz to 4.4 GHz, GPS-Disciplined OCXO, Reconfigurable USRP Software Defined Radio Device - The USRP-2952 provides an integrated hardware and software solution for rapidly prototyping high-performance wireless communication systems. Built on the LabVIEW reconfigurable I/O (RIO) architecture, USRP RIO delivers an integrated hardware and software solution, so researchers can prototype faster and shorten time to results. You can prototype a range of advanced research applications that include multiple input, multiple output (MIMO); synchronization of heterogeneous networks; LTE relaying; RF compressive sampling; spectrum sensing; cognitive radio; beamforming; and direction finding. The USRP-2952 is equipped with a GPS-disciplined 10 MHz oven-controlled crystal oscillator (OCXO) reference clock. GPS disciplining delivers improved frequency accuracy and synchronization capabilities.
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NI-9145, 8-Slot, Zynq-7020 FPGA, EtherCAT CompactRIO Chassis
784756-01
8-Slot, Zynq-7020 FPGA, EtherCAT CompactRIO Chassis - The NI‑9145 is a rugged EtherCAT slave chassis for adding deterministic, distributed I/O to any CompactRIO, PXI, or industrial controller with two Ethernet ports. You can program the chassis using Scan Mode for fast expansion of your real-time system or using the onboard FPGA for inline processing and high-speed I/O and control. You can daisy chain multiple NI‑9145 slave chassis from the master controller to expand time-critical applications to higher channel counts while maintaining hard determinism with minimal processor resources.
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FPGA Toolkits & IP
Curtiss-Wright Defense Solutions
Our tools and source code for use with our Xilinx Virtex and Kintex-based FPGA products include- FusionXF simplifies the development of FPGA-based application code by allowing developers to concentrate on their application without needing to worry about system integration of the hardware and operating system interface. The DDC family of IP cores supports decimation from 2 to 64 in complex mode and 2 to 32 in real mode
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PCIe-7822, Kintex 7 325T FPGA, Digital Reconfigurable I/O Device
785360-01
The PCIe‑7822 is a reconfigurable I/O (RIO) device that features a user-programmable FPGA for onboard processing and flexible I/O operation. With LabVIEW FPGA, you can individually configure the digital lines as inputs, outputs, counter/timers, PWM, encoder inputs, or specialized communication protocols. You can also program custom onboard decision making that executes with hardware-timed speed and reliability. Each line offers software-selectable logic levels. The PCIe‑7822 is well-suited for a wide variety of applications, such as high-speed waveform generation, sensor simulation, hardware‑in‑the‑loop (HIL) test, bit error rate test, and other applications that require precise timing and control.
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FPGA Mezzanine Card
FMC165
The FMC165 provides two 14-bit analog-to-digital (A/D) channels supporting RF sampling at 2.6 GSPS and one 14-bit digital-to-analog (D/A) channel with sampling rates up to 5.2 GSPS (2.6 GSPS direct RF synthesis). The converters are clocked by either an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. In addition, a trigger input for customized sampling control is available to users.
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400 MHz to 4.4 GHz, GPS-Disciplined OCXO, Reconfigurable USRP Software Defined Radio Device
783151-01
400 MHz to 4.4 GHz, GPS-Disciplined OCXO, Reconfigurable USRP Software Defined Radio Device - The USRP-2952 provides an integrated hardware and software solution for rapidly prototyping high-performance wireless communication systems. Built on the LabVIEW reconfigurable I/O (RIO) architecture, USRP RIO delivers an integrated hardware and software solution, so researchers can prototype faster and shorten time to results. You can prototype a range of advanced research applications that include multiple input, multiple output (MIMO); synchronization of heterogeneous networks; LTE relaying; RF compressive sampling; spectrum sensing; cognitive radio; beamforming; and direction finding. The USRP-2952 is equipped with a GPS-disciplined 10 MHz oven-controlled crystal oscillator (OCXO) reference clock. GPS disciplining delivers improved frequency accuracy and synchronization capabilities.
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Virtex-5 FPGA with Plug-in I/O
PMC-VFX
Acromag’s PMC-VFX boards feature a reconfigurable Xilinx® Virtex™-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCI-X interface. Field I/O interfaces to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine plug-in I/O modules.
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Gage EXpert FPGA Realtime Data Streaming
eXpert Stream-to-Analysis
All Gage PCI Express CompuScopes are able to Stream waveform data through the PCI Express bus directly to PC RAM. By contrast, older Memory Mode operation required storage of data in dedicated digitizer memory prior to data transfer. Streaming provides two distinct advantages over Memory Mode. First, Streaming may overcome the acquisition time limit imposed by the volume of dedicated digitizer memory. Second, in Streaming Mode, the user does not need to await completion of waveform acquisition before accessing the resulting waveform data, which is necessary in Memory Mode.
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3U CompactPCI Serial FPGA 10-20 ports Industrial Ethernet
SY7-CYCLONE
The EKF SY7-CYCLONE is a CPCI Serial FPGA board with front panel connectors for up to 20x100Mbps SPE ports. It can be configured as Ethernet NIC, switch, router, or gateway.
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Mezzanine FPGA I/O Module
ADC-MOD2
Curtiss-Wright Defense Solutions
Simple analog input to a processor is no longer enough. Software Defined Radio (SDR), RADAR, and telecommunications applications demand closely coupled high performance processing.
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PXIe-7820, Kintex 7 160T FPGA, 128 DIO, PXI Digital Reconfigurable I/O Module
783484-01
Kintex 7 160T FPGA, 128 DIO, PXI Digital Reconfigurable I/O Module—The PXIe‑7820 is a reconfigurable I/O (RIO) device that features a user-programmable FPGA for onboard processing and flexible I/O operation. With LabVIEW FPGA, you can individually configure the digital lines as inputs, outputs, counter/timers, PWM, encoder inputs, or specialized communication protocols. You can also program custom onboard decision making that executes with hardware-timed speed and reliability. Each line offers software-selectable logic levels. The PXIe‑7820 supports peer‑to‑peer streaming for direct data transfer between PXI Express modules. The PXIe‑7820 is well-suited for a wide variety of applications, such as high-speed waveform generation, sensor simulation, hardware‑in‑the‑loop (HIL) test, bit error rate test, and other applications that require precise timing and control.
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PCIExpress Kintex UltraScale FPGA Carrier Board
PCU: 085/115
The PCU continues DEG’s commitment to delivering high performance processing solutions for mission critical applications requiring the latest in AMD Kintex UltraScale FPGA computing power. The PCU is a PCIExpress, standard form factor , FPGA processor board designed to meet the needs of challenging, embedded high-performance digital signal processing applications at a competitive price point. AMD Kintex UltraScale XCKU085/115 delivers impressive processing capabilities and supports operations such as: FFTs, FIR filters, fixed-point and repetitive processing tasks. The PCU FPGA node processes input from the FMC HPC +(Vita 57.4) site, allowing for maximum application configurability and performance when coupled with DEG’s market leading ADC and DAC FMC modules (250MSPS to 12.0GSPS).
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4-Channel 200 MHz A/D with DDC, Virtex-6 FPGA - 6U VPX
Model 57661
- Complete radar and software radio interface solution- Supports Xilinx Virtex-6 LXT and SXT FPGAs- Four 200 MHz 16-bit A/Ds- Four multiband DDCs (digital downconverters)- One multiboard programmable beamformer- Up to 2 GB of DDR3 SDRAM; or: 32 MB of QDRII+ SRAM- PCI Express (Gen. 1 & 2) interface up to x8- Sample clock synchronization to an external system reference- LVPECL clock/sync bus for multiboard synchronization- Optional LVDS connections to the Virtex-6 FPGA for custom I/O- Ruggedized and conduction-cooled versions available- Synchronize up to eight modules with Model 7893 System Synchronization and Distribution Amplifier - PCIe
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PXIe HSS Optical FPGA Board
PXIe-8324
The Conduant PXIe-8324 Optical FPGA board provides the user with a hardware platform that is able to sustain full-duplex high-bandwidth transfers through its 8-lane Gen3 PXI Express (PXIe) interface and its 24-lane optical interface.
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PLD For Bridging, Infinitely Reconfigurable I/O Expansion.
MachXO
*Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM*SRAM based logic can be reconfigured in milliseconds using JTAG port*IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS*Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting*Available in TQFP, csBGA, caBGA and ftBGA packages
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Quad Serial FPDP Interface with Virtex-6 FPGA - 3U VPX
Model 52611
- Complete serial FPDP solution- Fully compliant with VITA 17.1 specification- Fiber optic or copper serial interfaces- Up to 2 GB of DDR3 SDRAM- PCI Express interface up to x4- LVDS connections to the Virtex-6 FPGA for custom I/O- 3U VPX form factors provides a compact, rugged platform- Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX™ System Specification)- Ruggedized and conduction-cooled versions available
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PCIe FPGA Carrier For FMC+, Altera Arria-10 GX1150
PCI536
The PCI536 is based on the Altera Arria-10™ GX1150 FPGA in F1517 package. The FPGA interfaces directly to the FMC+ DP 0-23 (single connector) and all FMC+ LA/HA/HB pairs, making it compatible with a wide range of industry standard VITA 57 modules. The PCI536 has x8 PCIe edge connector routed to the FPGA PCIe Gen3 hard IP block. It also has interface to two DDR4, 64-bit wide, with 16 GB total memory. This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.
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FPGA Digital IO XMC
XF07-523
Curtiss-Wright Defense Solutions
The XF07-523 is a rugged Kintex-7 FPGA based XMC with digital IO. The combination of direct high-speed I/O ports and FPGA processing makes the XF07-523 ideal for demanding applications including radar, imaging and test equipment across commercial and defense market spaces. The XMC form-factor is ideal to SWaP constrained platforms such as UAVs and fighter aircraft.
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FPGA Workbench and I/O Cards
FPGA Workbench software provides a complete development environment for building customized solutions based on Concurrent’s programmable FPGA cards. FPGA Workbench includes a powerful GUI for selecting and configuring a wide range of pre-developed data acquisition and industry-specific modules to meet your application requirements. The library of functional IP modules includes pulse width modulation, analog I/O, digital I/O, SENT protocol, encoder, ignition, injection, crank/cam shaft, wheel speed sensor and change-of-state.
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FPGA PXIe High-Performance Digital I/O Card
GX3700e
The GX3700e is a user configurable, FPGA–based, 3U PXI Express card offering 160 digital I/O signals which can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which can support SerDes data rates up to 1.2 Gb/s, digital I/O clock rates of 700 MHz, and features over 45,000 logic elements and 1.836 Kb of memory. The GX3700e is supplied with an integral expansion board providing access to the FPGA’s 160 I/Os. Alternatively, users can design their own custom expansion cards for specific applications - eliminating the need for additional external boards which are cumbersome and physically difficult to integrate into a test system. The design of the FPGA is done by using Altera’s free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded directly into the FPGA or via an on-board EEPROM.
