Arasan Chip Systems, Inc.
Arasan Chip Systems is a leading provider of Total IP solutions for mobile storage and connectivity applications.
- 408-471-4416
- 408-282-7800
- sales@arasan.com
- 2150 N. First St.
Suite 403
San Jose, CA 95131
United States of America
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PCIe End Point IP Core
The Arasan PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.
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USB Solutions
Arasan Chip Systems provides a complete suite of USB-compliant IP including low speed, high speed and super speed USB products. Arasan became a member of the USB-IF standards body in 1996 and delivered its first USB 1.0 IP product in that year. The offering expanded to USB 2.0 products in 2000 and USB 3.0 products in 2009. Arasan's customer base includes many major systems and SoC companies in variety of industries.
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MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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MIPI I3C Sensor Controller
I3C
The main purpose of MIPI I3C is to standardize sensor communication, reduce the number of physical pins used in sensor system integration and support low-power, high-speed and other critical features supported by I2C and SPI.
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Controller IP
ONFI – NAND
Continuous leadership in standards development and extensive customer adoption of previous versions ensures that Arasan has the knowledge and expertise to deliver compliant products with superior customer support. Extensive experience and compliance testing with all versions of ONFI specifications make the choice of Arasan ONFI NAND flash controller the lowest risk approach to implementation of ONFI enabled products. Arasan’s development engineering team provides direct support to customers ensuring that the highest level of knowledge is immediately available to the customer thus reducing problem resolution time.
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MIPI Total Display IP Solution
DSI
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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Total Solution
SD 4.1 Family
To meet the ever increasing data transfer rate in high end applications, such as professional broadcasting transmission or advanced high resolution display, the SD 4.1 specification calls out the maximum performance of 1.56 Gbps at UHS-II full duplex mode per lane or half duplex UHS-II at 3.16 Gbps. In real applications, due to the system overhead and different SD 4.1 device controller designs, the actual measured performance can vary dramatically from system to system. With the newly introduced ADMA 3, the OS driver is now able to issue multiple read or multiple write commands at once, without having to wait for the SD controller to complete one command at a time. Once the SD host controller has collected multiple commands, it will then manage and complete them without intervention from the host software drive. Thus, the UHS-II 1.56 Gbps interface can be more effectively utilized and maximize the system throughput. This feature can be very useful when running multithreaded applications where multiple applications are constantly updating their status or swapping their contents by writing or reading small chunk of data to or from the memory card.
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SD Card V.4.1 & UHS-II PHY
SD 4.1 Total Solution
To meet the ever increasing data transfer rate in high end applications, such as professional broadcasting transmission or advanced high resolution display, the SD 4.1 specification calls out the maximum performance of 1.56 Gbps at UHS-II full duplex mode per lane or half duplex UHS-II at 3.16 Gbps. In real applications, due to the system overhead and different SD 4.1 device controller designs, the actual measured performance can vary dramatically from system to system. With the newly introduced ADMA 3, the OS driver is now able to issue multiple read or multiple write commands at once, without having to wait for the SD controller to complete one command at a time. Once the SD host controller has collected multiple commands, it will then manage and complete them without intervention from the host software drive. Thus, the UHS-II 1.56 Gbps interface can be more effectively utilized and maximize the system throughput. This feature can be very useful when running multithreaded applications where multiple applications are constantly updating their status or swapping their contents by writing or reading small chunk of data to or from the memory card.
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End Point IP Core
PCIe
The highly configurable PCIe End point IP core supports x1, x2, and x4 lane with a selection of 32/64-bit data path. Depending on design requirements, a maximum of 8 VCs and 8 TCs are supported. The IP core consists of many useful features that can be included to enhance system performance and to address special design needs in different applications. The data link layer allows the configuration of infinite credits to boost the flow control efficiency. By-pass mode, cut-through mode, and store-and-forward mode are other optional items. The transport layer features include configurable ECRC generation and checking, support for up to 64 configurable outstanding non-posted requests, and configurable payload size from 128 to 4 Kbytes
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Universal Flash Storage
UFS
Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data storage. The UFS is also adopted by MIPI as a data transfer standard designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, DSC, PMP, MP3, and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. USF transfers follow the SCSI model, but with a subset of SCSI commands.The Arasan UFS IP family consists of Host controller IP, Device controller IP, and MPHY.
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MIPI SLIMbus
A typical mobile device has many low-speed/bandwidth peripherals connected to the host processor, which include microphones, speakers, sensors and many others. There is a need for a standard bus that enables multiple audio channels, peer-peer communications and lower pin count on the host processor. The MIPI alliance has defined the SLIMbus specification which provides a standard, robust, scalable, low-power, high-speed, cost-effective, two wire multipurpose interface that supports a wide range of digital audio and control solutions for mobile terminals.
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Arasan PHY IP
Arasan PHY’s are readily available and in production with multiple foundries from 16nm to 180nm. Our PHY’s are designed for low power on the most advanced nodes for the mobile market while also targeting the automobile market on specialized nodes where extreme temperature tolerance is required.
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MIPI Radio Front-End
RFFE
Mobile phone radios have developed into highly complex, multi-band and multi-standard designs that often have multiple radio frequency (RF) signal chains. The MIPI Alliance Specification for RF Front-End Control Interface (RFFE) was developed to offer a common and widespread method for controlling RF front-end devices. The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
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EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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Semiconductors
Meets SDIO card v2.0 specificationSupports SDIO SPI, 1-bit, and 4-bit SD modesHost clock rate from 0-50 MHzSingle SDIO function interfaceSD commands processed in hardwareReset output on completion of initializationIndication of high speed and high power enabling to application logicMaximum block size supported is 1024 bytesThree I/O mode selection pinsCRC7 and CRC16 modulesSupports direct R/W (IO52) and extended R/W (IO53) commandsAPB bus interfaceParallel bus interfaceStandard 8051 split bus interfaceGeneric 8051 bus interfaceUART interface
