JEDEC
semiconductor test methods and standards setting organization, Joint Electron Device Engineering Council.
See Also: UFS
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ESD & Latch-Up Test Service
MASER Engineering has automatic test equipment for the most common ESD test pulse models. MIL - JEDEC - ESDA - IEC standards. IC level Human Body Model. IC level Machine Model. IC level Charged Device Model. System level IEC 61000 HBM. AEC-Q100 Field Induced Gate Leakage test. Static Latch-Up test. Dynamic Latch-Up test.
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Detective Logic Analyzer
LPDDR3
Provides logic analyzer like deep transaction Listing and Waveform captureCan store up to 1G of captured States at 1600MT/sContinuous, real time analysis, not post-processingEye Detector guarantees valid data acquisitionExtensive Triggering and Storage Qualification allows precise insightProtocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specificationsMode Register Listing providedSupports Auto-Clock rate detect and clock stoppageConnects to the target under test with Flying Lead, BGA interposers or a midbus probeIntegrated Microsoft Charts gives quick insight into large trace capturesTrigger In & Out allows the Detective to integrate with other test tools
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SD Card
SD Card v.3.0 / eMMC v.4.51 IP Family
Designed for embedded applications that require high performance, small form factor, and high storage capacity, eMMC provides the support for embedded mass storage memory on embedded host systems. The eMMC protocol simplifies the access to NAND flash memories (such as MLC) to the host by hiding the functional differences among suppliers. Compliant to the latest JEDEC eMMC specifications, Arasan’s eMMC IP supports power-on-booting without the upper level software driver. The explicit sleep mode allows the host to instruct the controller to directly enter the sleep mode. The interface supports interface voltage of either 1.8V or 3.3V.
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Detective Logic Analyzer
DDR3
Provides logic analyzer like deep transaction Listing and Waveform captureCan store up to 1G of captured StatesContinuous, real time analysis, not post-processingEye Detector guarantees valid data acquisitionExtensive Triggering and Storage Qualification allows precise insightProtocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specificationsRow Hammer Analysis for potential data corruptionInteractions among up to 8 ranks, over two slots are analyzed.Mode Register Listing providedSupports Auto-Clock rate detect and clock stoppage Connects to the target under test with DIMM, SO-DIMM, and BGA interposers or a midbus probeIntegrated Microsoft Charts gives quick insight into large trace capturesTrigger In & Out allows the Detective to integrate with other test tools
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HBM Discharge Simulator
PSD-510
The PSD-510 is a low cost, light weight, battery powered Human Body Model (HBM) simulator designed to help customers determine the HBM ESD sensitivity of a device in accordance with ANSI/ESDA/JEDEC JS-001.
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Warpage Metrology System
TableTop Shadow Moiré (TTSM)
Measure warpage of substrates up to 300mm x 310 mm (a 300mm wafer or two JEDEC trays) with the entire measurement taking less than two seconds. Whether individual parts or a JEDEC tray of multiple parts, the TTSM provides an ultra-fast and highly accurate measurement at room temperature that is suited for tabletop use.
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Programmable Read Only Memory (PROM)
Is a Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM,EPROM, EEPROM and RAMs.
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IP Solution
eMMC 5.1
Demand for mobile content capacity and bandwidth for video, pictures and music is ever increasing. To address this demand in the next generation of smartphones, tablets, and portable devices, the eMMC 5.1 Specification from JEDEC, improves the current HS400 speeds operating at 3.2Gbps, with "command queuing" making the data transfers highly efficient by offloading the software overhead into the controller. eMMC 5.1 further improves the reliability of operation by utilizing an "enhanced strobe" at the PHY layer. The eMMC5.1 is backward compatible with the existing eMMC 4.51 and eMMC 5.0 Devices.
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Sideband Bus Protocol Analyzer
FS2700 DDR5
The FS27xx DDR5 Sideband Bus Protocol Analyzer is the latest DDR5 tool from FuturePlus Systems. FuturePlus has taken the complexity of 8 different JEDEC specifications and ported them into this very useful tool. DDR5 Validation Engineers and system integrators will not have to comb through complex specifications defining thousands of bits and register addresses. The tool takes care of this. Please request our data sheet for more information.
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test measurement unit
ITC59100 Rg/Qg
The ITC59100 Test Measurement Unit (TMU), which plugs into the ITC59000 Test Platform, performs gate charge (Qg) measurements that conform to MIL-STD-750C, Notice 2, Method 3471 and JEDEC Standard JESD24-2. In addition the ITC59100 TMU performs an internal gate resistance (Rg) test method that conforms to JEDEC Standard JESD24-11.
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LPDDR
A large number of LPDDR sockets have been developed to cover the wide variety of ball I/O configurations. This catalog supports the JEDEC 209 Standard configuration.
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mSAT SSD for Industrial Embedded Applications
mSATA SSD Series
ADLINK’s mSATA SSD Series with the SATA 6Gb/s interface is fully compliant with the standard mSATA form factor, also known as JEDEC MO300. Utilizing Toggle 2.0 MLC flash technology, capacities of up to 1TB are available with support for read/write speeds of up to 550MB/sec and 500MB/sec respectively . Additionally, the power consumption of the ADLINK’s mSATA modules is much lower than that of traditional hard drives.
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Flash SATA Disk /mSATA SATA 3 SLC,MLC
FSA 300 Series
*SATA III (6.0Gb/s) interface*Capacity: SLC 1 GB to 64 GB, MLC 4 GB to 128 GB*iSMART disk health monitoring*Intelligent error recovery system*Write protection security*Anti-vibration mechanical design*Excellent data transfer speed*Zero mechanical interference*JEDEC standard MO-300B dimension
