Verification IP
test and verify SoC's protocols and interface buses.
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STP Engine (IP Core)
The Stream Transpose® (STP) engine is a reconfigurable processor (DRP: Dynamically Reconfigurable Processor) core that combines the flexibility of software and the speed of hardware. The firmware defining processing can be reconfigured in an instant, allowing an almost infinite variety of functions to be integrated into a system. A 40nm process is currently available for ASIC.
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I/P Electro-Pneumatic Signal Converters
TEIP11 / TEIP11-PS
Electro-pneumatic signal converters are the link between the control rooms and pneumatic actuators. I/P converters are available with and without booster stage.
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IP Networking
We are the industry leader in IP Networking testing. We have a strong and wide-reaching industry reputation and participates in many industry organizations including the IETF, the IPv6 Forum, Open Networking Foundation and NetSecOPEN.
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RTL Floorplanner, Partitioning, And Floorplan Verification
ConStruct
ConStruct is an early RTL Floorplanner, partition explorer, and floorplan verification tool. It can further be used to generate the partitioned RTL based on specified criteria.
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FPGA Image Processing (IP) Development Kit
ProcVision
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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Vision Standard IP Cores
S2I’s Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.
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IP and Port Monitoring Software
CallerIP
IP and Port monitoring. See all incoming and outgoing connections made to your computer. Including process names, remote and internal port numbers and much more. Automated alerts bring your attention to illegal connections. Automated Alerting. Set up alerts to warn you of intruders and hack attempts. CallerIP can send an email, display a warning dialog and/or append a log file. CallerIP Server. CallerIP server allows you to view all incoming and outgoing connections to your computer from any browser in the world. CallerIP plots all connecting IP locations on a world map. IP origin shown on world map. All connecting IP address locations are shown on a world map.
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IP Reuse
IC Manage Global Design Platform (GDP & GDP-XL) includes an open platform for maximizing IP reuse. Design and verification teams can use the system to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems. ”
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Periodic Verification System for Measuring Static Charges and Verifying Ionizer Performance
STME-PVS
Statclean Technology (S) Pte Ltd
This meter is designed to measure static charges and to verify ionizer performance. It consist of three components- an Electrostatic Fieldmeter, a Detachable Plate and a Charger.
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ARINC 818-2 IP Core
iWave’s ARINC IP core is ARINC 818–2 compliant offering point-to-point, high-speed, low latency video transmission. This IP core can be implemented on any transceiver-based FPGA device. It can be used for both transmit and receive applications. This core supports configurable ADVB video formats and uses a simple streaming interface to interface with video & image processing IP cores supported by FPGA vendors.
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IP VIDEO MARGIN TESTER
IPMT-3
The IPMT-3 is a precision attenuator used to test IP video systems to insure that you have an adequate digital signal margin. Digital signal margin is the amount of signal level above the digital cliff that you have in your system to prevent a picture failure from occurring. IP cameras will give you a perfect picture until the network cable loss reaches beyond the minimum allowable signal level and then you suddenly get no picture at all. This effect is called the digital cliff, because like walking off of a cliff, everything is great till you take the last step off the edge and then all is lost.
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FPGA Toolkits & IP
Curtiss-Wright Defense Solutions
Our tools and source code for use with our Xilinx Virtex and Kintex-based FPGA products include- FusionXF simplifies the development of FPGA-based application code by allowing developers to concentrate on their application without needing to worry about system integration of the hardware and operating system interface. The DDC family of IP cores supports decimation from 2 to 64 in complex mode and 2 to 32 in real mode
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Real-time IP network measurements
IPProbe
Real-time network measurements for multiple IP interfaces. Detection of Packet loss, IAT (Inter Arrival Time), Delay, Bitrate and ETR290 problems. Stable packet generation and receiving is a key feature required in any modern IPTV environment. Any irregularity and/or discontinuity in this packet stream means buffering problems or losing frames. IP jitter provides a means to see the distribution and stability in the IP stream.
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Integrated Solution for Digital Switching & Fiber Optics Operational Verification
VERTA
When incorporated into defense/aerospace ATE, Verta enables reliable, error-free bus communication and interoperability tests to verify performance of high-speed, optically networked military weapon assemblies.
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MIPI Total Display IP Solution
DSI
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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Quad IP Carrier Module With Rear I/O
DP-cPCI-5121
DP-cPCI-5121 IP carrier board provides an electrical and mechanical interface for four industry standard IP modules. The board provides full data access to the IP modules I/O, ID and memory spaces. The programmable registers are used for configuring and controlling the operation of IP modules.
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EBIRST 200-pin LFH Verification Fixture
93-002-101
The 93-002-101 200-pin LFH Verification Fixture is an accessory for the eBIRST range of USB controlled test tools capable of performing automated path resistance tests on Pickering Interfaces switching solutions.. The tool simply interfaces with the switching system's connector so a test can be run using the supplied Windows-based software.
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8 inch CCTV Tester & ip Camera Tester
Fuzhou Metricu Technology Co Ltd
8 inch IP camera tester M-IPC-800C with analog, HD-TVI, HD-CVI, AHD, cable tracer app with toner wand, anti-sunlight and screen protecting cover, video level meter for for analog camera, TVI camera, CVI camera, AHD camera.
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96 Channel I/O and 64 Channel I/P VME Module
DP-VME-3132
The DP-VME-3132 provides 96 channel RS422 differential digital I/Os and 64 channel RS422 differential isolated inputs on the front end and rear side. On the rear side, it is interfaced with the VME 64x backplane.
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IPS BEACON
The Flowserve IPS Beacon is a data acquisition, logging and visual alert device that monitors process pump health. Mounted atop the pump bearing housing, the intrinsically safe Beacon checks power-end vibration (x-y-z axis) and temperature against pre-set limits, logging this data with a time and date stamp when an alert situation occurs.
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IP X7, X8 - Waterproof Test Chamber
The IP X7 and IP X8 test equipment simulates the water immersion environment to test the water resistance and sealing of the samples during storage, transportation and usage. It is widely applied to electrical and electronic products, lamps and lanterns, electrical cabinet, electrical components, automobile, motorcycle and its spare parts and other products. It provides the basis to improve the performance of the products.
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4x4 HDMI Matrix Switch with RS232 and IP Control
HSM-I-04-04
4x4 HDMI matrix switch with RS232 and IP control. Supports HDCP, deep color, multi-channel digital audio (up to 7.1 channels), and may be used with any combination of DVI (PC) or HDMI (HDTV) sources and displays.
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HDMI Audio Extractor with Audio Amplifier, RS-232 and IP Control
EMX-I-AMP
The EMX-AMP is a 4K HDMI Audio Extractor with built-in 50 watt audio amplifier for direct connection of 8 ohm speakers. The device also provides line-level stereo Aux audio input and allows audio mixing of HDMI audio with the Aux input. Volume can be controlled from the front panel, RS-232, or external digital rotary pot (encoder) that can be mounted on a wall-plate.
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Audio IP
We provide high-performance, compact, low power and customizable audio analog mixed-signal IP in leading foundry processes, including a wide range of ADC, DAC, CODEC and Voice Activity Detectors.
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Enhance Transactional Universal Verification Methodology (UVM) testbenches
TrekUVM
TrekUVM automatically generates self-verifying test cases that run in existing transactional testbenches, including those compliant with the Universal Verification Methodology (UVM) standard. This verifies your chips more quickly and more thoroughly than using UVM alone to generate transactions. TrekUVM's generated test cases target all aspects of full-chip verification and work in a variety of different environments.
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Radio over IP Testing
The transmission of data over the new generation of digital radio communications is proving increasingly popular with the emergency services, government, security, transport, construction, exploration, utilities and military sectors. However, RoIP/IP over Radio systems are frequently deployed in extremely challenging conditions such as natural disasters, storms, blackouts, difficult terrains (mountains, tall buildings) etc. Therefore, it is imperative that such systems are thoroughly tested prior to live deployment to ensure they will work effectively in potentially “life or death” situations.
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Wireless IP Surveillance Camera
ENVIROMUX-IPCAM-W
View and control the camera from the ENVIROMUX web interface, the camera web interface, included software, or with a compatible cell phone. With the ENVIROMUX-2D/5D/16D, a triggered snapshot can be forwarded in alert e-mails. A snapshot can be triggered by any programmed event (motion detection, door open/close, glass break, smoke, liquid detection, etc.). Image sensor: 1/4" progressive scan CMOS sensor. Video Streaming: simultaneous Motion JPEG and MPEG-4. Frame rate: 30fps at 640x480 (VGA) resolution. Lens: F2.0, 4.0 mm (0.16 in). RJ45 connector. Wireless models: wireless IEEE 802.11 b/g up to 54 Mbps. Regulatory approvals: CE, FCC, RoHS.
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Verification Suite
Cadence is committed to providing industry-leading bare metal compute, the fastest verification engines, and the smartest verification applications so you can find and fix the most bugs per dollar compute per day.
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Rapita Verification Suite
RVS
*Run requirements-based tests on your code *Produce coverage evidence including MC/DC from tests *Analyze execution time including worst-case timing on-target *Understand program scheduling behavior *Produce evidence for DO-178 and ISO 26262 certification
