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Compiler
translates a programming language to machine code.
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Deep Packet Inspection
FlowPro
FlowPro is inserted into areas of the network when visibility is needed. It uses a deep packet inspection (DPI) to compile a flow cache, and exports traffic and threat details reflecting 100% of all communications that pass by. FlowPro is a great complement to the Scrutinizer Incident Response System and ensures the security team has insight where they need it.
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Smart Analysis for PHP
PHPSA
PHPSA is a development tool aimed at bringing complex analysis for PHP applications and libraries.*Static analysis*Code metrics*Branch prediction*Sandbox (AST) Compiler
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MEMS Testing System
BK3010V2
The BaKo BK3010V2 is our updated MEMS Tester, based on our C-Mic tester, the best selling BK3010. It's small enough to carry under your arm and with a test time of under 0.5 seconds, it tests as fast as you can connect a microphone. Setting up the specifications is very easy and can be done in a few minutes. In addition, the new BK3010V2 can be connected to a computer so you can keep and view compiled data and track trends in variations in your C-Mics.
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Welcome To GLCD Font Creator V1.0.0
GLCD Font Creator is the ultimate font creation utility for embedded systems. It lets you create fonts for Liquid Crystal Displays (LCD) and Graphic LCD. It provides a very nice and intuitive user interface. GLCD Font Creator lets you create fonts and symbols from scratch, or by importing existing fonts on your system. It lets you modify and adjust them for your needs, apply effects to them, and finally export them as source code for use in your favorite language compiler.
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Human Vibration Management Software
HVManager
HVManager is a Risk Assessment and Recordkeeping software tool for reporting Vibration measurements and predicting Personal Exposure Levels. It provides reports of vibration measurement data from hand-arm and whole-body measurements acquired from the Larson Davis HVM100 Human Vibration Meter and produces vibration database records by tool type and serial number. HVManager also compiles cumulative predicted vibration exposure levels from any combination of tools and task durations taken from the measurement database.
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Automatic Constraints Compiler & Manager
ConMan
ConMan is the first commercially available formal constraints compiler tool that automatically generates SDC for any level of hierarchy and for any mode of a SoC, thereby significantly shortening the timing closure cycle. ConMan provides an intuitive means of automatically compiling and managing sign-off quality correct-by-construction timing constraints for all applications.
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TTCN-3 Compilation & Execution Environment
Titan
Titan is a TTCN-3 compilation and execution environment with an Eclipse-based IDE. The user of the tool can develop test cases, test execution logic and build the executable test suite for several platforms. TTCN-3 is a modular language specifically designed for testing (the acronym itself stands for Test and Test Conformance Notation), standardized by ETSI (see www.ttcn-3.org) and endorsed by ITU.
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Cloud Platform
Wind River® Studio Cloud Platform is an open source, production-grade distributed Kubernetes solution for managing edge cloud infrastructure. Based on the OpenStack StarlingX project, the cloud platform in Studio represents a compilation of best-in-class open source technology that delivers the features needed to effectively deploy and manage distributed networks.
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Elvior TestCast
TTCN-3
Elvior TestCast is a TTCN-3 test development and execution platform which includes TTCN-3 editor, TTCN-3 compiler and TTCN-3 executive. TestCast can be used for testing software or hardware components in a wide range of industry sectors. Candidate systems for testing with TestCast can be found from the industry sectors where TTCN-3 is widely used as an accepted generic test language - telecommunication, IOT, transport and automotive, military and defense. TestCast is ideal for incremental project development. It can be used for testing of an individual task or process. One can continue with the integration tests of a subsystem consisting of processes and later to integrate those subsystems and test them together as a whole software subsystem. It is even possible to continue to perform software/hardware integration tests where TestCast can be used to test software embedded in target hardware.
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FPGA PXI High-Performance Digital I/O Card
GX3702
The GX3702 is a user configurable, FPGA-based, 3U PXI card which offers 160 digital I/O signals which can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which can support SerDes data rates up to 1.2 Gb/s, digital I/O clock rates of 700 MHz, and features over 45,000 logic elements and 1.836 Kb of memory. The GX3702 is supplied with an integral expansion board providing access to the FPGA's 160 I/Os and is pin for pin compatible with the NI PXI 7813R and 7811R FPGA cards . Alternatively, users can design their own custom expansion cards for specific applications - eliminating the need for additional external boards which are cumbersome and physically difficult to integrate into a test system. The design of the FPGA is done by using Altera's free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded into the FPGA directly or via an on-board EEPROM.
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FPGA PXI High-Performance Digital I/O Card
GX3700
The GX3700 is a user configurable, FPGA-based, 3U PXI card which offers 160 digital I/O signals which can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which can support SerDes data rates up to 1.2 Gb/s, digital I/O clock rates of 700 MHz, and features 47,500 logic elements and 2.1 kb of memory. The GX3700 is supplied with an integral expansion board providing access to the FPGA’s 160 I/Os. Alternatively, users can design their own custom expansion cards for specific applications - eliminating the need for additional external boards which are cumbersome and physically difficult to integrate into a test system. The design of the FPGA is done by using Altera’s free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded into the FPGA directly or via an on-board EEPROM.
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Standard Resistor Oil Bath
9400
Measurements International Ltd.
Measurements International’s series of fluid baths are used for the maintenance of standard resistors and shunts. The 9400 has been designed after compiling years of customer feedback on existing resistor oil baths.
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Compilers
Compilers for PIC, dsPIC/PIC24, PIC32, ARM, AVR, FT90x, 8051; GUI Development Software.
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16-Axis PCIe EtherCAT MainDevice Motion Controller
PCIe-8332
ADLINK PCIe-8332 is a hardware-based EtherCAT motion controller able to support up to 16 synchronized axes and over 10,000 points simultaneously. The PCIe-8332 features dedicated isolated emergency stop input (EMG), and configurable isolated high-speed digital input as not only generic sensor input but also pulsar input, with up to 1MHz input frequency. Optimum jitter control is provided in minimal cycles of 250µs to optimize synchronous I/O performance for vertical automation applications in semiconductor, electronic manufacturing, and others. The PCIe-8332 provides an out-of-shell application-ready (APS) function library to generate multi-dimensional, highly synchronized, time-deterministic event-triggered motion & I/O control. A wide range of compatible 3rd party SubDivice are easily designed with ADLINK's APS function library. ADLINK's MotionCreatorPro 2 utility is fully compliant with the Microsoft Windows environment, that allows complete EtherCAT motion and I/O configuration and function evaluation as well as compiling program download functions.
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ML/AI Low Power FPGA
iCE40 UltraPlus
*Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/O, up to 80 kbits of embedded dual port memory and 1 Mbit of embedded single port memory*Ultra-low power advanced process with static current as low as 75 uA and 1-10 mA active current for most applications*High performance signal processing using DSP blocks with multiply and accumulate functions*Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation*FPGA design tools, demos and reference designs to kick start designs
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Time Domain Replication (Road Load Simulation)
The powerful graphical editor makes it easy to review and compile your field sample data for use in the test lab. The point editor, filters, velocity and displacement compensation ensure the test feasibility is evaluated at an early stage. The continuous closed-loop controller then replicates the test files with very high levels of precision. The control algorithms use a continuous coherence averaging technique to ensure a stable proactive control loop that will not only provide accurate replication but will also respond to changes in test item dynamics.
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Lattice SensAI Studio
Graphical interface based tool to help users built accelerated machine learning applications quickly. Select from a range of models pretrained to cover popular use cases, bring in your own data for additional training, validation the quality of training using TensorBoard, compile for Lattice’s FPGAs*Model Zoo with variety of models based on multiple architecture*Easy to use labeling, training, and compilation GUI*Docker container provided for installation on your own machine or server*Free license
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FPGA Image Processing (IP) Development Kit
ProcVision
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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Free Imperas RISC-V Instruction Set Simulator
riscvOVPsim
*RiscvOVPsim - RISC-V Instruction Set Simulator (ISS) - fast, simple, easy to use, cross software development for embedded systems*The riscvOVPsim ISS is an ideal starting point for an embedded software development project. *RiscvOVPsim allows the development and debug of code for the target RISC-V processor on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running riscvOVPsim with an argument to specify the name of the application object.
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Harmonics And Flicker Measuring System
ProfLine Series
The Teseq ProfLine system is a complete and cost effective Harmonics and Flicker measurement test system which compiles to the latest IEC/EN standards, including IEC 61000-3-2 and IEC 61000-3-3. The programmable power generation capability of up to 45 kVA (90 kVA and 145 kVA sources comprise multiple 45 kVA units) provides more than ample power to cater for a wide range of Equipment Under Test (EUT).
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Integrated Development Environment
All Cosmic C Cross Compilers for Windows include IDEA - Cosmic's own integrated development environment which is preconfigured for the the compiler it comes with. IDEA is designed specifically for developing embedded applications with Cosmic compilers. IDEA integrates an editor, project manager, graphical smart build/make facility, program analyzer, link file generator, documentation manager and ZAP debugger into one easy to use environment running under Windows Windows 7, XP and compatible. IDEA includes the following features:
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Rapidly Compile Networks For Implementation On Lattice SensAI IP Cores
Neural Network Compiler
Analyze networks for fit in the chosen number of engines and allocated memory. After compilation, simulate networks for functionality and performance prior to testing in hardware. Graphical display of networks supports analysis and understanding.
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The Imperas Instruction Set Simulator
ISS
The Imperas ISS is often the first simulation product used in an embedded software development project. The Imperas ISS allows the development and debug of code for the target architecture on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.
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Byte Craft Compilers
Byte Craft has been producing a select range of highly optimised compilers and development tools since 1976. The current processor targets are shown below. Byte Craft is, like Phaedrus Systems heavily involved in the international standards panels for C.
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Visual Designer For Arduino™
AVR And Raspberry Pi®
Proteus Visual Designer combines world class Proteus VSM simulation with an easy to use flowchart editor and a gallery of virtual hardware to provide a truly integrated and intuitive development environment for Arduino and Raspberry Pi. The peripheral gallery makes hardware design easy. Simply add a shield or sensor from the gallery and Visual Designer will automatically place the correct circuitry on the Proteus schematic for you and add some simple methods to Visual Designer that allow you to control the hardware. The software is then designed as a flowchart so you can easily drag and drop these methods along with decisions, delays and assignments to drive the hardware. Compile and simulate at the press of the button, making use of our renowned simulation and debugging technology to watch your design come to life on screen.Finally, transfer to the physical hardware with a single mouse click and see it working first time in the real world.
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Development System
FE-RE2
* Emulates Atmel AT89C51IE2/RE2 and others * 128K Code Memory * Real-Time Emulation * Frequency up to fmax 60 MHz * 3V and 5V Support * ISP and X2 Mode Support * Windows Debugger For C, C++ and Assembler * RS-232 and USB Interface * C Compiler and Assembler
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Wireless Fiber Inspection Probe
OCI-20BN-W
OCI-20BN-W is a portable optical fiber connector inspector for checking fiber and connector end-face cleanliness, ideal for bench top and fiber optic network installation technicians to eliminate error caused by poor quality or improper cleaning.OCI-20BN-W offers excellent viewing on connector/fiber end-face and is able to feature to record and save image/video of fiber end-face; It can be connected to PC or phone by WIFI.More than 40 assorted high-precision tips designed for inspection solutionsAngled/Lengthened tips for awkward positions.Connect smart phone for testing FiberEye2 is the application on an android or IOS smart phone to capture, display and record the fiber end-face image from the Wi-Fi probe.Connect tablet/laptop for testing EFD is the analysis software on Windows tablet/laptop to have dusts, and scratches on end face inspected, analyzed, compiled and reported
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Ada Development Environment
GNAT Pro
GNAT Pro is a robust and flexible Ada development environment. It comprises a full Ada compiler (Ada 83, Ada 95, and Ada 2005 features) based on the GNU GCC technology, an Integrated Development Environment (GNAT Programming Studio), a comprehensive toolsuite including a visual debugger, and a set of libraries and bindings.
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SystemVerilog, VHDL & Unified Power Format (UPF) Parser Platforms
Verific Design Automation, Inc.
SystemVerilog (which includes Verilog 2001) and VHDL are parsed and processed in two steps, analysis and elaboration. Mixed VHDL and SystemVerilog compilation is fully supported. UPF is processed in a single step, analysis.
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In-Circuit Emulator - 80C186/80C188 Family
DS-186
* Support for 80C186/8/XL/EA/EB/EC, 8086/8, V20/25/30/40/50 and other Microprocessors * Full-speed Emulation up to 25MHz * 1MB of Zero-Wait-State Mapped Memory * 8K x 32-bit Frames Dynamic Trace Buffer * 1MB Hardware Breakpoints * 115 KBaud RS-232 Communication Link * Numeric Coprocessor Support * OMF Converter * Support for Borland, Microsoft and Intel Compilers * Full Support for C, C++, Pascal and Assembler
